1. FIELD OF THE INVENTION
This invention relates to an instruction processor having a plurality of address adders and in particular to an instruction processor suitable for processing branch instructions which perform operations for register operands and at the same time perform address calculations for branch destination instructions.
2. DESCRIPTION OF THE RELATED ART
In an instruction processor to which this invention is applied, an instruction is treated in five cycles, D, A, L, E, and P. In the D cycle, decoding of the instruction and address calculations therefor are performed; in the A cycle a memory operand is fetched from the buffer storage; in the L cycle a fetched operand is transmitted; in the E cycle necessary predetermined operation by the instruction is executed; and in the P cycle the result of the operation is written in a general-purpose register. As a method for advancing address calculations for a succeeding instruction, in the case where the succeeding instruction utilizes the content of the general-purpose register changed by a preceding instruction in an instruction processor, heretofore it has been proposed in Japanese Patent Unexamined Publication No. 41641/79, to dispose a simple auxiliary arithmetical or logical operation unit (ALU) apart from the main ALU, to process the instruction changing the content of the general-purpose register with a high speed in the auxiliary ALU unit, and to input the result of the operations not through the general-purpose register but directly in the address adder so that it can be utilized for the address calculations for the succeeding instruction. In this case, the operation by the auxiliary ALU is performed in the E cycle of the auxiliary ALU, which cycle is earlier by one cycle than the E cycle for the main ALU to perform the operation. However, since the succeeding instruction cannot begin its D cycle immediately after the end of the D cycle of the preceding instruction until the end of the execution in the auxiliary ALU there has been an overhead in the D cycle.